Time efficient embedded EEPROM/processor control method

ABSTRACT

In an embedded system with a processor and an EEPROM that provides an EEPROM BUSY signal if the EEPROM is in a write mode, a block-before-write subroutine is used to hold the processor before a write operation to the EEPROM. A detector circuit finds read functions that are to be mapped into the EEPROM address space and suspends code execution if an EEPROM BUSY bit is asserted and the EEPROM is the read target. Code execution by the processor and processor access to memories other than the EEPROM is permitted while the EEPROM is being written. If any access is made by the processor to the EEPROM while the EEPROM BUSY bit is asserted, the processor enters a WAIT state to temporarily suspends execution of program code.

TECHNICAL FIELD

The invention relates to an embedded system that includes anelectrically erasable programmed read only memory (EEPROM) and anassociated processor and, in particular, to improving the performance ofan embedded system.

BACKGROUND ART

An embedded system is generally a specialized computer system thatperforms a special purpose and that may be a subsystem in a largersystem. Often, an embedded system is provided on a single, inexpensiveintegrated circuit chip that includes a microcontroller ormicroprocessor and associated memory. The associated memory includes anEEPROM and other types of memories. A write operation for an EEPROMtakes much greater time than a read operation for an EEPROM. A typicalwrite time for an embedded EEPROM is several milliseconds, while atypical read time is 10 to 100 nanoseconds. As a consequence of thegreater write time for an EEPROM, a typical processor that is associatedwith an EEPROM in an embedded system is required to stop and then wait aconsiderable amount of downtime for each write operation to the EEPROM.

A typical EEPROM write operation includes the following steps: a pagebuffer for the EEPROM is loaded with one or more bytes of data. Avoltage on a control pin is changed to start the write operation bywriting from the page buffer to the memory cells. Upon completion of thewrite operation, an EPROM BUSY bit is reset to indicate completion ofthe EEPROM write operation.

In a typical embedded EEPROM, the EEPROM is not available for read/writeoperations until the EEPROM BUSY bit is reset, or goes away. Thisresults in the processor waiting (either by polling the EEPROM BUSY bit,or by an interrupt) until EEPROM BUSY bit is reset before continuingcode execution. This is especially true in systems where code and dataare stored in a single EEPROM. Requiring the processor to wait is verycommon in embedded systems where both program code and data are storedin a single EEPROM.

In an embedded system that has more than one type of memory, read/writeoperation can be optimized in such a way that the processor can continueto do useful work during the time that the EEPROM is in a write cycle.Such optimizations should make sure that, during the write operation, noEEPROM accesses will be needed by the computer. This requires that thecomputer does not fetch data from the EEPROM while EEPROM BUSY bit isasserted. In an embedded system, it can become complicated trying tomake such an optimization.

Alternatively, a simpler block-after-write approach is often used towrite data into an EEPROM and then to block operation of themicroprocessor while the write operation to the EEPROM is beingcompleted. An example of code for a block-after-write subroutine isshown below: // example of block-after-write code void eeWriteByte(uint16_t address, uint8_t data) { outb(IO_EECR, EEWRITE_FLAG; // set theEEPROM write bit in the control register outw (IO_EEAR, address); //write the address to the EE address register outb(IO_EEDR, data); //write the data to the EE data register outb(IO_EECR, 0); // drop thewrite control line starting the write while(inb(IO_EESTATUS) &EEBUSY_FLAG) { nop( ); // wait until busy goes away } }

FIG. 1 is a flowchart 100 for a block-after-write subroutine thatblocks, or interrupts, operation of a computer after writing to anEEPROM. Block 102 shows that the block-after-write subroutine first setsthe EEPROM WRITE bit in the control register. Block 104 shows that thesubroutine then writes the designated EEPROM address to the EEPROMaddress register. Block 106 shows the subroutine then writes the data tothe EEPROM data register. Block 106 shows that a WRITE CONTROL line isdropped to start writing the data from the EEPROM data register into theaddressed EEPROM memory location. Block 110 indicates that the processoris blocked from operation by being in a wait state until the EEPROMwrite operation is complete and the EEPROM BUSY bit is deasserted.

At first thought you could move the blocking code to the beginning ofthe subroutine, but it has the result that any subsequent EEPROM readswould fail. Incorrect data would be read without any indication an errorhad occurred.

U.S. Patent Publication 2004/0208064 to Sohn et al. describes a methodof controlling an IC memory that is capable of simultaneously performinga data read operation and a data write operation. However, this approachrequires a memory with separate input and output pins and also uses atag memory. Using additional hardware would not be cost effective in aembedded microcontroller system.

U.S. Pat. No. 5,657,467 to Hasegawa describes a non-volatilesemiconductor memory device that includes a separate register forstoring data. A selection circuit is supplied with a busy signal from awrite control circuit, which indicates that the memory device isoperating in a write mode and that an output signal from the separateregister should be used. Having a separate register for storing datawould not be cost effective in a embedded microcontroller system.

U.S. Pat. No. 6,512,693 to Honda et al. describes a memory cell arraythat is arranged into a number of cores, each of which includes a blockof memory cells. A number of cores are selected as a first bank, whilethe remaining cores are selected as a second bank. This allows a dataread operation to be carried on in one bank while a data write/eraseoperation is carried out in the second bank. Having a number of coresand block of memory would not be cost effective in an embeddedmicrocontroller system

What is needed is an efficient technique for effectively reducingdowntime for a processor associated with an EEPROM in an inexpensiveembedded system.

SUMMARY

Writing data into an EEPROM takes a significant amount of time. Thepresent invention addresses the problem of a processor that isassociated with an embedded EEPROM that is required to wait aconsiderable amount of downtime for each write operation into theEEPROM. The present invention is intended to effectively reduce downtimefor the associated processor (reduces processor latency). The presentinvention is intended to assist an embedded processor to concurrentlyexecute program code while an associated EEPROM is being written into.

The present invention uses a block-before-write subroutine to check andwait if the EEPROM is busy before a write operation to the EEPROM. Thepresent invention also provides a circuit that detects reads that areintended to be mapped into the EEPROM address space and that suspendscode execution if an EEPROM BUSY bit is asserted. As a consequence, thepresent invention allows program code execution by the associatedprocessor and access to other memories, that is, to memories other thanthe EEPROM, even while the EEPROM is being written. If any access ismade by the processor to the EEPROM, the processor enters a wait stateand the processor temporarily suspends execution of program code untilthe EEPROM BUSY bit is deasserted.

This circuit in combination with the block-before-write code allows forprogram-code optimization without being concerned with unanticipatedEEPROM accesses. The result is that program code execution by thecomputer continues until an EEPROM BUSY signal blocks operation of theprocessor. The present invention provides both a block-before-writefunction and a hardware read lockout. As a consequence, write operationsto the EEPROM are blocked at the start of a write subroutine, while theread operations to the EEPROM are blocked by the additional circuit.

The present invention provides a time-efficient read/write controlmethod for an embedded EEPROM and processor. The method includesproviding an active EEPROM BUSY signal that is active, or asserted, whenthe EEPROM is engaged in a write activity. When an EEPROM BUSY signal isinactive, or deasserted, the method continues to execute program code inthe processor. When the EEPROM BUSY signal is active, the method blockswrite code execution at the start of a write subroutine. Also when theEEPROM BUSY signal is active, the method includes blocking read codeexecution by using a read detection circuit that detects when the EEPROMBUSY signal is active and when a read is requested for an EEPROMaddress. After the EEPROM BUSY signal is inactivated, or deasserted, themethod includes continuing code execution by the processor until anEEPROM BUSY signal blocks code execution such that write operations areblocked at the start of a write subroutine while read operations areblocked by the read detection circuit.

The method includes detecting a read address that is mapped into theEEPROM address space. As long as the EEPROM is not accessed by theprocessor and the EEPROM BUSY signal is not asserted, program codeexecution is allowed.

The step of blocking write code execution at the start of a writesubroutine when the EEPROM BUSY signal is active includes: detectingsetting, or asserting, of an EEPROM BUSY in a control register; blockingcode execution in the processor; waiting until the EEPROM BUSY bit isdeasserted, or inactivated; writing an address to an EEPROM addressregister; writing data into an EEPROM data register; and toggling awrite control line to start writing data into the EEPROM at the addressEEPROM address register.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart for a conventional block-after-write subroutine.

FIG. 2 is a block diagram of an exemplary microcontroller having abuilt-in EEPROM.

FIG. 3A shows an EEPROM address register for the microcontroller of FIG.2.

FIG. 3B shows an EEPROM data register for the microcontroller of FIG. 2.

FIG. 3C shows an EEPROM control register for the microcontroller of FIG.2.

FIG. 4 is a flow chart for a block-before-write subroutine.

FIG. 5 is a circuit diagram for a read detector circuit.

DETAILED DESCRIPTION

FIG. 2 shows the architecture of an exemplary AT90S1200 RISCmicrocontroller 200 produced by ATMEL Corporation that has a built-inEEPROM. The microcontroller 200 uses a Harvard architecture concept withseparate memories and with buses for program and data memories. An 8-bitdata bus 202 is shown linking various internal components. 32×8 generalpurpose registers 204 provide two output operands to an arithmetic logicunit (ALU) 206. Program memory is provided as an in-system downloadable512×16 programmable FLASH memory 208. During interrupts and subroutinecalls, a return address program counter (PC) is stored in the stack,which is a 3-level deep hardware stack 210 dedicated for subroutines andinterrupts.

This microcontroller contains 64 bytes of data in a 64×8 EEPROM memory212 that is organized as a separate data space in which single bytes canbe read and written. Access between the EEPROM and the CPU is controlledby EEPROM control registers 214 that are provided in an I/O space.Various I/O locations in the I/O space are accessed by IN and OUTinstructions that transfer data between the 32 general working registers204 and the I/O space. EEPRM write access time is in the range of 2.5 to4 milliseconds. A self-timing function lets user software detect whenthe next byte can be written to the EEPROM. When the EEPROM is read orwritten, the CPU is halted for two clock cycles before the nextinstruction is executed.

FIG. 3A illustrates an 8-bit EEPROM address register (EEAR) 300 for themicrocontroller 200. The EEAR 300 has an I/O space address of $1E. Bits0-5 (EEAR0-EEAR5) specify the EEPROM addresses in the 64-byte EEPROM 212space.

FIG. 3B illustrates an 8-bit EEPROM data register (EEDR) 310 for themicrocontroller 200. The EEDR 310 has an I/O space address of $1D. Bits0-7 (LSB-MSB) contain data for the EEPROM 212. For an EEPROM writeoperation, the EEDR register 310 contains the data to be written to theEEPROM 212 in an EEPROM address given by the EEAR register 300. For anEEPROM read operation, the EEDR register 310 contains the data read outfrom the EEEPROM 212 at the EEPROM address given by EEAR 300.

FIG. 3C illustrates an 8-bit EEPROM control register (EECR) 320 for themicrocontroller 200. The EECR 320 has an I/O space address of $1C.

Bit 1 of the EECT 320 is an EEPROM Write Enable (EEWE) bit, which is thewrite strobe to the EEPROM 212. When the address and data are correctlyset up, the EEWE bit is set to write into the EEPROM. When the writeaccess time has elapsed, the EEWE bit is cleared, or reset to zero byhardware. User software can poll this bit and wait for a zero beforewriting the next byte. When EEWE has been set, the CPU is halted for twocycles before the next instruction is executed.

Bit 2 of the EECT 310 is an EEPROM Read Enable (EERE) bit, which is theread strobe to the EEPROM 212. When the correct address is set up in theEEAR 300, the EERE bit must be set. When the EERE bit is cleared, orreset to zero by hardware, requested data is found in the EEDR 310. TheEEPROM read access takes one instruction and there is no need to pollthe EERE bit. When the EERE bit has been set, the CPU is halted for twocycles before the next instruction is executed.

An example of code for a block-before-write subroutine is shown, below.// example of block-before write code void eeWriteByte( uint16_taddress, uint8_t data) { while(inb(IO_EESTATUS) & EEBUSY_FLAG) { nop( );// wait until busy goes away } outb(IO_EECR, EEWRITE_FLAG; // set theEEPROM write bit in the control register outw (IO_EEAR, address); //write the address to the EE address register outb(IO_EEDR, data); //write the data to the EE data register outb(IO_EECR, 0); // drop thewrite control line starting the write }

FIG. 4 is a flow chart 400 for a block-before-write subroutine that hasthe computer wait until the EEPROM is clear before writing into theEEPROM. Block 402 detects setting of an EEPROM BUSY bit in the controlregister. Block 406 indicates that the computer waits until the EEPROMwrite is completed. Block 408 write an address to the EEPROM addressregister. Block 410 writes data into the EEPROM data register. Block 412toggles a write control line to start writing data into the EEPROM atthe specified EEPROM address.

FIG. 5 shows a READ DETECTOR circuit 500 that includes an EEPROM ADDRESSdetector 502 that monitors addresses in the address space of the EEPROMin which a read is to be mapped. If such an address is found, a READDETECT output signal is provided on a signal line 504 to one inputterminal of a 2-input logic AND gate 506. The other input terminal ofthe 2-input logic AND gate 506 receives an EEPROM BUSY signal from themicrocontroller 200 with the built-in EEPROM. If both the READ DETECTsignal and the EEPROM BUSY signal are present at the same time, the ANDgate 506 provides a WAIT signal on WAIT signal line 508 back to theprocessor in the microcontroller 200. Code execution and memory accessescan continue as long as they do not try to access the EEPROM. If anyreads try to access the EEPROM, code execution is postponed via the waitmechanism, which is common to most processors.

The READ DETECTOR circuit 500 circuit in combination with theblock-before-write code allows code optimization without being concernedwith unanticipated EEPROM accesses. The result is that program code isable to continue execution in the processor until an EEPROM BUSY signalblocks execution. Write operations are blocked at the start of theblock-before-write subroutine while reads are blocked by the additionalREAD detector circuit 500. Depending on the degree of code optimization,the present invention combination can eliminate some or all of the longswait times by letting the EEPROM write while program code executioncontinues concurrently.

The present invention allows program code execution by the processor andmemory accesses, other than to the EEPROM, by the processor to continueas long as the code execution by the processor and memory accesses bythe processor do not try to access the EEPROM itself. If any read doestry to access the EEPROM, the program code execution is postponed bymeans of a processor WAIT mechanism, which is common to most processors,miocrocomputers, or microcontrollers. The READ DETECTOR circuit 500 incombination with the block-before-write code allows code optimizationwithout having to be concerned with unanticipated EEPROM accesses. Theresult is that code is able to continue execution in the processor untilan EEPROM BUSY signal blocks execution of the code. For a busy EEPROM,write operations are blocked at the start of the subroutine, while readoperations are blocked by the READ DETECTOR circuit 500.

The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical application,to thereby enable others skilled in the art to best utilize theinvention the various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the claims appended hereto and theirequivalents.

1. A time-efficient read/write control method for an embedded EEPROM andprocessor, comprising the steps of: providing an EEPROM BUSY signal thatis active when the EEPROM is engaged in a write activity; executingprogram code by the processor when the EEPROM BUSY signal is inactive;blocking write code execution by the processor at the start of a writesubroutine when the EEPROM BUSY signal is active; blocking read codeexecution with a read detection circuit that detects when the EEPROMBUSY signal is active and when a read is requested for an EEPROMaddress; and continuing program code executing by the processor when theEEPROM BUSY signal is inactive, where the EEPROM BUSY signal blocks codeexecution such that write operations are blocked at the start of a writesubroutine and such that read operations are blocked by the readdetection circuit only when the read operations result in EEPROM readduring an active EEPROM BUSY signal.
 2. The method of claim 1 whereinthe step of blocking read code execution by using a read detectioncircuit that detects when the EEPROM BUSY signal is active and when aread is requested for an EEPROM address includes detecting a readaddress that is mapped into the EEPROM address space.
 3. The method ofclaim 1 including allowing code execution by the processor and accessesby the processor to memory other than the EEPROM to continue as long asthe EEPROM is not accessed by the processor and the EEPROM BUSY signalis inactive.
 4. The method of claim 1 wherein the step of providing anEEPROM BUSY signal from the EEPROM when the EEPROM is in a writeactivity includes providing the EEPROM BUSY signal as the state of anWRITE BUSY bit.
 5. The method of claim 1 including embedding the EEPROMand processor together in an embedded system in a singleintegrated-circuit package.
 6. The method of claim 1 wherein the step ofblocking write code execution at the start of a write subroutine whenthe EEPROM BUSY signal is active includes: detecting asserting of anEEPROM BUSY bit in a control register; blocking code execution in theprocessor; waiting until the EEPROM BUSY bit is deasserted; writing anaddress to an EEPROM address register; writing data into an EEPROM dataregister; and toggling a write control line to start writing data fromthe EEPROM data register into the EEPROM at the address written in theEEPROM address register.
 7. A time-efficient control method for anembedded EEPROM and processor, comprising the steps of: reading andwriting the EEPROM with the processor; asserting an EEPROM BUSY signalby the EEPROM when the EEPROM is in a write mode of operation; using ablock-before-write subroutine for the processor to suspend codeexecution by the processor if the EEPROM BUSY signal is asserted;detecting a read address that is mapped into the EEPROM address space;suspending code execution by the processor if a read address which ismapped into the address space of the EEPROM is detected and if theEEPROM BUSY signal is asserted; and allowing code execution by theprocessor and accesses by the processor to memory other than the EEPROMto continue as long as the EEPROM is not accessed by the processor andthe EEPROM BUSY signal is not asserted.
 8. The method of claim 7 whereinthe step of asserting the EEPROM BUSY signal by the EEPROM when theEEPROM is in a write mode of operation includes providing the EEPROMBUSY signal as the state of an WRITE BUSY bit.
 9. The method of claim 7wherein the EEPROM and processor are embedded in a singleintegrated-circuit package.
 10. The method of claim 7 wherein the stepof using a block-before-write subroutine for the processor to suspendcode execution by the processor if the EEPROM BUSY signal is assertedincludes: detecting asserting of the EEPROM BUSY bit in a controlregister; blocking code execution in the processor; waiting until theEEPROM BUSY is deasserted; writing an address to an EEPROM addressregister; writing data into an EEPROM data register; and toggling awrite control line to start writing data from the EEPROM data registerinto the EEPROM at the address written in the EEPROM address register.